The present invention is directed to a switching network for digital switching systems composed of switching matrices having their respective inputs connected parallel.
Such a switching network or a partial switching network can, as FIG. 1 also shows, be composed of switching matrices having m inputs and at least one output or a plurality of outputs that is lower in comparison to the plurality of inputs. Inputs of the same standing in these switching matrices are connected to one another. The plurality of switching matrices connected to one another is dependent on how many outputs the switching network or partial switching network has. In the case of a quadratic arrangement having m inputs and m outputs and switching matrices having only one output as illustrated in FIG. 1, m such switching matrices are connected parallel.
FIG. 2 shows an example of a switching network or a partial switching network having m inputs and outputs, whereby the plurality of inputs of a switching matrix is less than m. Given the assumption of e inputs per switching matrix, m/e groups of arrangements according to FIG. 1 are provided in this case, their outputs of the same standing being respectively combined by one of m multiplexers MUX1 through MUXm to form m overall outputs.
A plurality of such partial switching networks according to FIG. 1 or FIG. 2 are connected to one another via one or more space switching stages for constructing even larger switching networks.
FIG. 3 shows the internal structure of a switching matrix of a type employed in the arrangement of FIG. 1. The illustrated unit has m inputs E1 through Em and, correspondingly, m frame memories R1 through Rm that are connected to the inputs by serial-to-parallel converters S/P1 through S/Pm. Given the assumption of pulse frames having n channels, the frame memories have n memory locations for respectively one PCM (pulse code modulated) word.
The write-in into the frame memories occurs cyclically, to which end a counter Z supplies n write-in control addresses as well as a write enable signal W to respective memory cells of the same order of all frame memories via a decoder D1. The read-out from the frame memories occurs randomly, to which end a holding memory H that is also cyclically driven by a counter Z via a decoder D2 supplies read-out control addresses. The read-out control addresses have two parts together with a read instruction signal R, namely a partial address AP that identifies memory locations within the frame memories and a partial address AR that identifies the individual frame memories. The memory location partial addresses AP likewise simultaneously proceed via the decoder D1 to memory locations of the same rank in all frame memories, by contrast whereto the memory block partial address AR proceeds via a decoder D3 for the drive of respectively one of the frame memories to a corresponding read enable input thereof.
The aforementioned counter Z supplies 2 n drive addresses for n channels during the duration of a pulse frame, these drive addresses being accompanied in alternation by the write-in instruction signal W and the read instruction signal R. An AND operation of the write-in instruction signals with the drive addresses accompanying them by an AND element K leads to the forwarding of these addresses via the aforementioned decoder D1 to the frame memories as write-in control addresses. Negation of the read instruction signals R by a negator N and subsequent AND operation with the read control partial address AR supplied from the holding memory, likewise by the AND element K, leads, as an alternative thereto, to the forwarding of these read control partial addresses to the individual memory cells of all frame memories, also via the decoder D1. The write-in instruction signal W acts as an enable signal for input circuits I1 through I3 via which information coming from the serial-to-parallel converters can proceed into the frame memories. The negated read instruction signal R also acts as an enable signal for the decoder D3 via which the second partial addresses AR proceed to the frame memories and, thus, enable the acceptance of information from respectively one of the frame memories at a parallel-to-serial converter P/S of the output side.
The events in time channel conversions with the described switching matrix shall be briefly set forth below.
Equivalent time channels of the input time-division multiplex lines connected to the inputs E1, E2 and Em are thereby considered, these having a time slot u and being referenced a in the case of the first input multiplex line, b in the case of the second input multiplex line and c in the case of the input multiplex line m. The channel a should be converted onto a channel y, and the channel b should be converted onto a channel z, and the channel c should be converted onto a channel x on the output multiplex line. Consequently, the respective addresses of the time slots u are entered as the first drive partial addresses AD in the memory locations of the holding memory H that correspond to the time channels x, y and z. The address of the memory m resides in the memory location corresponding to the time channel x as second partial address AR, the address of the memory 1 resides in the memory location corresponding to the time channel y, and the address of the memory 2 resides in the memory location corresponding to the time channel x.
The operations are then such that the contents of the channels a, b and c, according to their time slots u, are entered into the memory locations 1-u, 2-u and m-u of the frame memories 1, 2 and m that are allocated to these time slots, being entered therein during the course of the cyclical write-in. As a result of the random read drive of the frame memory 1 during the time slot y, of the frame memory 2 during the time slot z, and of the frame memory m during the time slot x, respectively with the memory location address u, the desired time channel conversion occurs. Thus, the time channel sequence c, a, b is provided on the output multiplex line with respect to the time channel a, b and c, as indicated in FIG. 3.
In the case of a switching matrix having, for example, two outputs, the holding memory would have to be read out twice per time slot for supplying the read control addresses for the frame memories, whereby the first read event supplies the information for the first output and the second read event supplies the information for the second output.
When, for forming a switching network, a plurality of switching matrices according, for example, to FIG. 2 are connected parallel at their input side, as shown, for example, in FIG. 1, then a write-in of the channel information a, b and c into the frame memories of all switching matrices ensues, even though a read-out in the assumed example only ensues from the frame memory of that switching matrix to which the appertaining output multiplex line is connected.
A fashioning of the switching network of LSI modules is of interest in view of achieving a cost-beneficial and space-saving structure of a switching network. An optimally great plurality of inputs and outputs is thereby desired, whereby, however, limits are established by the dissipated power of the module.